Performance-driven read-after-write dependencies softening in high-level synthesis

Conventional scheduling algorithms usually produce schedules whose cycle lengths are influenced by the operations latency. Operations are assigned to one or several consecutive cycles (multicycle operators) and one operation cannot begin until all its predecessors have finished, except for operations chaining. This technique allows the execution in the same cycle of several data-dependent operations, being some bits of the chained operations calculated in parallel. Chaining one operation to its predecessor requires the completion of both in the selected cycle. This paper presents a less restrictive technique based on the softening of the read-after-write dependencies among operations, which allows beginning the execution of one operation before the calculus of its predecessors has been completed. This becomes feasible when the execution of the predecessor has begun in the selected cycle or in a previous one, and even if it finishes in a posterior cycle. This design technique is applied before synthesis to transform behavioural specifications into new ones whose subsequent synthesis substantially improves circuit performance.