Analytic expression and approach for low subthreshold-swing tunnel transistors

Recent experimental demonstrations of interband tunnel transistors by Appenzeller [1], in carbon nanotubes, and simulations by Bhuwalka [2], of vertical Si/SiGe p-i-n interband tunnel transistors show that subthreshold swings of 40 mV/decade or less can be achieved in tunneling transistors. We derive here, a simple analytic expression for the subthreshold swing in tunnel transistors which shows that there are two physical mechanisms in tunnel transistors which can be optimized to achieve low subthreshold swings. Extending from this analysis we propose a new silicon-on-insulator tunnel transistor to achieve low subthreshold swing toward significantly lowering power in digital logic devices.