FPGA implementation of MMSE adaptive array antenna using RLS algorithm

A fixed-point RLS processor was simulated and integrated on a FPGA system. The proposed system including synchronization process and performance was confirmed from experiments in radio anechoic chamber and indoor propagation. This paper demonstrates the RLS processor integration system using modulated signals of /spl pi//4-DQPSK (/spl pi//4-differential quadrature phase shift keying). The performance of the RLS processor is verified by simulations and experiments.