A new readout-controller for COSY-DAQ based on the Virtex-II Pro /spl Gt/system on a chip/spl Lt/-FPGA

For the DAQ in hadron physics experiments at the 3.7 GeV storage ring COSY in FZ Julich a new generation of readout electronics has been implemented. High performance and cost efficiency is achieved by the definition of an optimized parallel backplane bus in the frontend, based on LVDS technology with 80 Mbytes/s nominal throughput. For the readout of the digitizing modules a systemcontroller module has been developed which operates as master of the backplane bus and transfers the acquired data to the upper layers of the DAQ system via optical links. The systemcontroller is based on the Virtex-II Pro Gtsystem on a chipLt-FPGA running embedded Linux on its internal PowerPC CPU. The framework of the third generation of DAQ at COSY is introduced and the architecture of the systemcontroller is described. Measurement-results of the communication link performance are presented