Low power processor design for wireless sensor network applications

These years, wireless sensor network (WSN) has emerged as an especially hot topic, which is the result of rapid advances in miniaturization, low-power circuit design, more energy-efficient wireless communication, improved small-scale energy supplies and reduced manufacturing costs. A WSN node consists of four basic components: sensing, data processing, communicating and power supply. Among these, low power technology is the spirit of WSN hardware and software design. In this paper, a novel WSN-oriented low-power processor (WO-LPP) design scheme is presented. Our processor has an 8-bit simple 3-stage pipeline event-driven RISC ISA core and 4k SRAM, 64K on-chip program flash connected by Harvard bus. At the same time, on-chip event-based task management, on-chip hardware management and power management scheme are coordinately designed with some general peripheral devices, such as time counter, real time counter, ADC, SPI, I/sup 2/C and UART interface to meet most application requirements of wireless sensor networks. An AES (advanced encryption standard) engine is also designed to address the security issue of wireless communication. Implement results show the processor is specially optimized for wireless sensor networks.