High density radiation hardened FeRAMs on a 130 nm CMOS/FRAM process

Using hardened-by-design techniques previously demonstrated on a 1-kbit prototype 0.35-micron ferroelectric semiconductor memory, an 8-kbit FeRAM memory segment has been designed for fabrication on a Texas Instruments 130nm commercial CMOS/FRAM process. The 8-kbit segment can be arrayed to provide radiation hardened ferroelectric memory densities up to 64 Mbit with reasonable chip sizes and radiation hardness vastly superior to that of flash memory. The 130nm CMOS/FRAM process is capable of wide signal margin, high endurance and long data retention, consistent with the demands of the space market. It is projected from radiation testing of the 1-kbit prototype FeRAM that TID radiation tolerance to greater than 1Mrad(Si) and SEL tolerance to greater than 75 LET can be obtained without the expense and complexity of SOI, and without the need for radiation shielding. A test chip for radiation evaluation has been designed that includes the 8-kbit memory segment, critical boost circuitry, I/O buffers and a number of discrete transistors and devices. The 100 by 300 micron 8-kbit memory segment incorporates a patented, rugged, shunted ferroelectric memory cell that uses a true and complement bit line architecture. The segment read access time is simulated to be 20ns, and read and write cycle times are simulated to be 45ns.