System-level test and yield improvement for optoelectronic-VLSI chips

Some of the unique issues involved in testing transmitter and receiver circuits for optoelectronic-very-large-scale-integrated (OE-VLSI) applications are reviewed. In particular, the problem of testing OE-VLSI chips prior to optoelectronic device integration is outlined. Based on circuit-level approaches such as fault sensitization and novel system-level testing methodologies, the first OE-VLSI chip with testable transmitters, receivers and digital circuitry was designed in 0.35-/spl mu/m CMOS. The operation of the ASIC was verified experimentally and a fault-coverage greater than 80% is obtained, for a test time in the hundreds of microseconds range. Yield improvements ranging from 10% to 25% are predicted.