Design and optimization of low-voltage low-power quasi-floating gate digital circuits

This paper explores the design and optimization of quasi-floating gate MOS techniques to low-voltage/low-power digital circuitry. The simulated power consumption of standard CMOS gates is compared to that of QFGMOS implementations in a 0.18/spl mu/m process for different supply voltages and device sizes. A 0.4V V/sub DD/ full-adder biased for propagation delay similar to that of 0.8V CMOS is simulated and shown to consume 1.2/spl mu/W for a 50MHz input, representing more than a 50% power reduction over the CMOS equivalent. A divide-by-16 circuit designed for operation at a maximum frequency of 400MHz uses 25/spl mu/W, 45/spl mu/W, and 75/spl mu/W for supplies of 0.4V, 0.6V and 0.8V.