A VLSI systolic filter with ternary coefficients for delta-modulated signals

The realization of a digital FIR (finite impulse response) filter for both input data and coefficients encoded with ternary levels by delta-sigma modulation (DSM) is described. Due to the ternary values, multibit calculations are not needed. The filter architecture is very regular, highly parallel, and pipelines. The filter is easily made adaptive, as coefficients can be changed during normal operation. It is composed of bit-level systolic arrays whose cells are designed to allow a working frequency and consequently a throughput rate close to the limit of the technology used. A filter with 160 taps was realized in a 3- mu m H-CMOS technology.<>