A theoretical discussion on performance limits of CMOS charge pumps

This paper presents a study of the theoretical performance of CMOS integrated charge pumps (CPs). The discussion is based on a behavioural model of the CP and a mathematical manipulation of power efficiency definition. The CP theoretical limit is found in terms of both power efficiency and maximum driving capability. The basic idea is to analyze the performance of any CP only considering the voltage gain, the output resistance, the number of capacitors and parasitic capacitances. Experimental results are presented to validate the theoretical analysis.