Complexity reduction in an nRERL microprocessor

We describe an adiabatic microprocessor implemented with a reversible logic, nRERL (Lim et al., 2000). We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption. We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25/spl mu/m CMOS technology. Its minimum energy consumption of 4.67/spl mu/A/MHz was measured at V/sub dd/=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version.