Design and modelling of a III/V mobile-gate with optical input on a silicon substrate

The co-integration of III/V devices such as InGaAsP PIN diode and an (In)AlAs/In(Ga)As Resonant Tunnelling Diodes with state-of-the-art silicon NMOS transistors is studied. The III/V devices layers are epitaxially grown and fabricated on silicon substrates for the extraction of model parameters. The performance of a potentially low-cost optical receiver circuit on silicon is simulated using HSPICE up to 10 Gb/s.