Concurrent error detection and fault location in reconfigurable WSI structures for FFT computation

Presents a novel approach for concurrent error detection and location in homogeneous VLSI/WSI (wafer scale integration) architectures for the computation of the complex N-point fast Fourier transform. The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analyzed with respect to functional and physical faults. Overhead issues for hardware and timing are addressed.<>