90 nm multi-level-cell flash memory technology

Intel's 90 nm flash technology delivers industry leading 0.076 /spl mu/m/sup 2/ flash single bit memory cell at 210 nm pitch which translates to 0.038 /spl mu/m/sup 2/ bit size with multi-level-cell (MLC), using 193 nm lithography and Cu interconnect [Y. Song (2003)]. The 193 nm lithography required significant etch improvement especially at flash gate patterning with multi-layer gate stack and contact patterning due to reduced etch selectivity to resist. The other technology enablers are advanced STI gap fill, improved process at self-aligned-polysilicon (SAP) polish to enable vertical scaling, improved oxidation for trench sidewall oxidation, advanced cleaning tool to reduce defects for data retention and cycling endurance, and improved contact patterning and dielectric strength film to endure the program/erase cycles at reduced contact to gate spaces.