An improved high performance CMOS second generation current conveyor

This paper deals with optimally sizing CMOS current conveyors. Both static and dynamic performances are improved. Current conveyor performances are improved thanks to an objective function which minimizes Rx input resistance, noise effects and occupied area. Also, it maximizes Ry, Rz output resistances and both voltage and current bandwidths. The ameliorated optimized structure presents very good performances: 2.6GHz and 3.9 GHz as current and voltage band width respectively and 18/spl Omega/ as Rx input port resistance value. PSPICE software simulation results are presented showing obtained results.