Models for embedded application mapping onto NoCs: timing analysis

Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of NoCs needs techniques for application cores mapping, allowing reducing the message latency and consequently the overall execution time. To obtain mappings that fulfill the requirements during high-level design, appropriate models for NoCs and application cores become mandatory. High abstraction levels modeling may lead to unreliable estimates. On the other hand, detailed models may imply complex algorithms and high computational effort, with unacceptable computation time to get satisfactory results. NoC modeling for latency estimation requires capturing some infrastructure characteristics like topology and routing policies. Application cores models have to capture the application behavior, in terms of computation and/or communication. For instance, communication weighted models (CWM) and communication dependence model (CDM) consider only application communication aspects. However, the communication dependence and computation model (CDCM) consider both aspects of an application. This work compares these three models, according to their algorithm complexity and accuracy to model the application performance. We show that depending on the application characteristics, one of the models can be more suitable than the others.