Systolic architecture for computing the discrete Fourier transform on FPGAs

A systolic architecture for calculating the discrete Fourier transform (DFT) is described which is based on a new matrix formulation that decomposes the transform into sets of 4-point transforms. The architecture supports transform lengths that are not powers of two or based on products of coprime numbers. Compared to previous systolic implementations, the architecture is computationally more efficient and uses less hardware. It provides low latency as well as high throughput, and can do both 1D and 2D DFTs. An automated CAD tool was used to find latency and throughput optimal designs that matched the target field programmable gate array structure and functionality.