Optimized design for high-speed parallel BCH encoder

A new design method for parallel BCH encoder is presented, which can eliminate the bottleneck in long BCH encoder. Based on serial LFSR architecture, a recursive formula which can deduce the parallel BCH encoder was first derived. The complexity and the delay of the critical paths of the circuit could be effectively decreased by using a tree-type structure, sharing sub-expression and limiting its maximum number, and balancing load technique. Finally, a parallel BCH (2184, 2040) encoder with 8-bit parallelism is realized in TSMC's 0.18 /spl mu/m CMOS technology for high-speed optical communication that can operate at 400 MHz and process data at the rate of 2.5 Gb/s.