Design rules to avoid tunnel cracking in VLSI interconnects during process flow

A failure analysis based on an energy approach is used to study a two metal level structure in VLSI interconnects. The failure scenario of a channel cracking at the interface low-k /TaNTa is treated for the first level. A finite element FE model has been developed which shows the impact of the layout and the process on the stress level and interface decohesion probability in this structure. In addition, some general design rules are deduced from these calculations to avert crack propagation in interconnects.