Low-power high-speed level shifter design for block-level dynamic voltage scaling environment

Two novel level shifters that are suitable for block-level dynamic voltage scaling environment (namely, V/sub DD/-hopping) are proposed. In order to achieve reduction in power consumption and delay, the first proposed level shifter which is called contention mitigated level shifter (CMLS) uses a contention-reduction technique. The simulation results with 65-nm CMOS model show 24% reduction in power and 50% decrease in delay with 4% area increase compared with the conventional level shifter. The second proposed level shifter which is called bypassing enabled level shifter (BELS) implements a bypass function and it is fabricated using 0.35/spl mu/m CMOS technology. The measurement results show that the power and delay of the proposed BELS are reduced by 50% and 65%, respectively with 60% area overhead over the conventional level shifter.