Low temperature wafer-scale 3D ICs: technology and characteristics

Fabrication techniques that allow wafer-scale transplantation, bonding and interconnecting of fully fabricated device layers with thickness on the order of micrometers are described. The temperature budget of this 3D integration technology is less than 350 /spl deg/C and the approach utilizes Benzocyclobutene (BCB) as the permanent wafer bonding medium. Alignment registration of several micrometers between donor device layer to the host substrate is achieved. The characterization of devices, structures and process conditions are presented. Also, measurement of heating effects and temperatures in a 3D IC environment is described. The 3D integration approach allows reduction in crosstalk for mixed-signal applications using inter-device layer ground planes. This technique shows -8 dB of crosstalk attenuation between device layers. The newly developed 3D integration fabrication methodology can be extended beyond silicon-based devices to SiGe and III-IV technologies.