A 1.6-GHz delta-sigma modulated fractional-N frequency synthesizer

The goal of this work is to design a high speed, low power consumption, and low noise RF frequency synthesizer. It can be applied to the RF front-end architecture of the IEEE 802.11 b/g channels. In this work, the VCO is an LC-tank oscillator to get the low noise performance, and an all digital delta-sigma modulator, which controls the divider of the synthesizer, is designed to present the channel selection and the fractional division ratio. Basing on the theory of phase-locked loop, the concepts, several different architectures, and the implementation of the fractional-N frequency synthesizer are given. The fractional-N frequency synthesizer is fabricated in a 1.8V, 0.18/spl mu/m CMOS technology, and consumes 29.05 mW in the operating frequency of 1.6 GHz.