An efficient and low power systolic squarer

Squarer has been extensively applied on image, video and data compression for portable devices. Thus, squarer with faster speed, smaller die size, and lower power is tremendously important practically. By carefully classifying the cells in straightforward systolic array into 5 groups and carefully design each cell by reducing the gate count of full adder and D flip flops, we proposed a new systolic squarer that outperforms the other circuits (Chun-Lung Shu and Wu-Hung Lu, 2003; Kolagotla et al., 1998; Dumonteix et al., 2001) on number of transistors, speed, power, and power/speed ratio. The design has been implemented on chip using TSMC 0.35 /spl mu/m 2P4M process.