Investigation of an advanced SiH/sub 4/ based self-aligned barrier process for Cu BEOL reliability performance improvement on industrial 110 nm technology

The paper deals with the introduction of an innovative self-aligned capping layer leading to the formation of a Cu/Si/N mixed interface. The process was first developed targeting the aggressive 65 nm technology node and below. After optimisation, the process was successfully introduced in a well known Cu/FSG integration scheme prior to SiN etch stop layer deposition; process interest and maturity was demonstrated on 300 mm wafers in a 110 nm technology node by showing both its full compatibility with industrial requirements for stabilized technology and clear performance improvements in terms of electrical performance, defectivity and resistance to electromigration. These results open large perspectives for the integration of a Si-based self-aligned barrier on Cu lines, the process capability covering several technology nodes used either in addition to thin dielectric barriers or as a single capping of the copper lines.