Automatic generated built-in-self-test for embedded memory

Embedded memory test is becoming an important issue in system-on-chip (SOC) development. Direct access of memory cores from the limited number of I/O pins is usually not feasible. Built-in-self-test (BIST) is rapidly becoming the most acceptable solution. A BIST design for embedded DRAMs is proposed. The BIST circuit is on-line programmable for its NPSF test algorithms. Experimental results show that the present BIST design is cost effective.