Hardware implementation of large number multiplication by FFT with modular arithmetic

Modular multiplication (MM) for large integers is the foundation of most public-key cryptosystems, specifically RSA, El-Gamal and the elliptic curve cryptosystems. Thus MM algorithms have been studied widely and extensively. Most of works are based on the well known Montgomery multiplication method (MMM) and its variants, which require multiplication in N. Authors have always avoided the fast Fourier transform (FFT) method believing that it is impractical for present system sizes despite its smaller complexity order. In this paper, the authors presented the design and hardware implementation of a FFT-based algorithm using modular arithmetic to efficiently compute very large number multiplications. The algorithm has been implemented in CASM, an intermediate level HDL developed in the laboratory. The target architecture is a FPGA. The algorithm is scalable and can easily be mapped to any operand size. Results show that such algorithm implementation starts to be useful for 4096-bit operands and beyond.