Efficient VLSI implementations of fast multiplierless approximated DCT using parameterized hardware modules for silicon intellectual property design

An efficient implementation of discrete cosine transform (DCT) computations are presented based on the so-called shifted discrete Fourier transform (SDFT), a generalization of the conventional DFT (DFT). Due to the simple form of the factorized matrices, the derived architecture can be easily constructed from the cascade of only two types of parameterized hardware modules: butterfly operators and rotators. The butterfly operator performs the conventional butterfly shuffling and addition/subtraction. The rotator that performs plane rotations of two-dimensional (2-D) vectors is designed using carry-save-adder (CSA)-based unfolded pipelined CORDIC architecture where the rotation angles can be approximated with different accuracies using a sequence of bipolar signs. The proposed one-dimensional and 2-D DCT implementations composed of the above two types of parameterized modules can be used as flexible and reusable Silicon Intellectual Property (SIP) for the DCT computation unit to be embedded in system-on-a-chip (SoC) design. The proposed implementations have many features and advantages, including SIP reusability, low complexity, high-throughput, regularity, scalability (easy extension of transform length), and flexibility (approximated DCT with various accuracies).