A silicon BiCMOS single-chip UHF receiver design

A single-chip UHF receiver integrated with PLL working at ISM band from 290 MHz to 470 MHz is presented. It operates from a single 5 V supply with a nominal current consumption of only 6.5 mA (with all parts of the receiver are active). The IC requires only a low frequency reference clock (crystal oscillator), a varactor diode, and a few standard passive elements to operate fully, satisfying almost all of the low power radio regulations. The LNA has a 1.56 dB noise figure, 15.2 dB power gain and 8 dBm IIP3. The mixer has a 9.3 dB SSB noise figure with 5 dBm IIP3. The PLL achieves a phase noise of -99.7 dBc/Hz at 100 kHz offset with 433 MHz carrier frequency. The RF receiver was implemented in a 0.8 /spl mu/m, 12 GHz f/sub T/ (NPN) Si BiCMOS production technology.