Impact of substrate bias on p-MOSFET negative bias temperature instability

The negative bias temperature instability (NBTI) of p-MOSFETs is an important reliability issue for digital as well as analog CMOS circuits. To date, characterization and modeling efforts to analyze the NBTI mechanism involve devices stressed with zero substrate bias (VB). However, many circuits utilize nonzero V/sub B/ to vary the device threshold voltage (V/sub T/), (e.g., for dual V/sub T/ CMOS, standby leakage reduction, etc.). This paper aims to systematically study NBTI for V/sub B/>0 V stress, which, to the best of our knowledge, has not been done so far. It is shown that NBTI increases for V/sub B/>0 V stress. This is attributed to enhanced interface (N/sub IT/) and bulk (N/sub OT/) trap generation due to impact ionization and hot-hole (HH) generation. The role of gate bias (V/sub G/), V/sub B/, temperature (T) and oxide thickness (T/sub PHY/) is studied. This work would help all efforts in determining: (i) reliability budget for any operating V/sub B/; (ii) proper choice of stress V/sub B/ during accelerated aging tests; and (iii) suitable TCAD and SPICE models.