New approach of 90nm low-k interconnect evaluation using a voltage ramp dielectric breakdown (VRDB) test

Due to the fact that the gap between adjacent structures decreases for advanced interconnect systems (90 nm), the characterization of the minimum space dielectric areas is of increasing interest. The most commonly used method to investigate these materials is the bias temperature stress (BTS, i.e., BEoL-TDDB)-test. This test covers diffusion driven effects. In very small dimensions, additional failure mechanisms can take place. These gate-oxide-like failures could result in reliability issues prior to the diffusion failures. Therefore, we have developed a new model to extrapolate breakdown voltage distributions to product lifetime requirements by voltage ramp dielectric breakdown (VRDB) tests. The calculation shows extreme voltage acceleration in combination with a very low temperature dependence. The area-scaling correlation and the very high sample size of actual 90 nm ICs allows a good calculation of the minimum median breakdown voltage (MVbr) necessary to meet the lifetime requirements regarding this failure mechanism.