Delay variation mapping induced by dynamic laser stimulation

We present a novel technique based on dynamic laser stimulation (DLS) to characterize CMOS structures and to highlight time margin alterations by delay variation mapping. We used photoelectric laser stimulation (PLS) or thermal laser stimulation (TLS) to perturb CMOS transistor characteristics in order to affect propagation delays. The proposed methodology further extends the capabilities of DLS techniques such as soft defect localization (SDL) and laser assisted device alteration (LADA) to characterize defective ICs.