Bake enhanced erratic behavior in gate stress characteristics in flash memories

Bake enhanced degradation of gate disturbance of flash cells has been studied. It is found that the worst-case situation exists when the cells are baked in the erased state. The number of cells appearing in the tail distribution can be three times as high when the cells are baked in the erased state than those cells baked in the programmed state. This bake state dependent gate stress behavior can be related to process induced mobile ions or to positive centers in the tunnel oxide.