Radiation-induced clock jitter and race

The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft error rate (SER) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SER if no mitigation techniques are applied. Our results show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20/spl times/ improvement in sequential SER as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty.