The impact of partially scaled metal barrier shunting on failure criteria for copper electromigration resistance increase in 65 nm technology

Previous technology nodes employing Cu interconnects have shown an abrupt increase in resistance (R), in excess of the conventional /spl Delta/R/R/sub 0/=20% R increase for the failure criteria (FC). We have observed a different behavior for 65 nm technology electromigration (EM) testing, in which the R increase is sloped after the initial step increase in R. The R step (R-step) increase is less than 20%, so that the sloped region (R-slope) occupies a portion of the 20% FC. We explain the two regions based on the full span void formation (R-step), followed by void growth along the length direction (R-slope). For the first time, we use this sloped region to obtain values for the EM activation energy (Q) and current exponent (n) of dual-damascene Cu interconnects, which agree very well with values obtained from the failure time associated with the initial R step. We propose a new FC corresponding to the time of the initial R-step increase. The increased importance of the R-slope region (RSR) arises from the partially scaled metal barrier thickness, which allows for increased current shunting in the barrier layer. These RSR effects will become even more evident in technology nodes beyond 65 nm.