Sampling rate conversion by Fourier interpolation

New time-domain SRC using Fourier interpolation to achieve less gate count than in frequency domain is proposed and implemented by FPGA. Layout area of the proposed SRC based on a 0.35/spl mu/m process is 5.728mm/sup 2/, smaller than the conventional SRC using filters. The noise level is reduced down to the quantization error level by using several improving methods.