Low power JPEG-2000 image compression for industrial embedded applications

In this paper we described an implementation for a dual JPEG-2000 entropy coder on FPGA and its integration within a JPEG-2000 software encoder on an industrial platform. The use of FPGA as coprocessor on an industrial platform dramatically improves the performance of the JPEG-2000 encoder especially the entropy coding phase. Implementation on a Xilinx XCV405E allows up to 2 parallel coders because of the important use of the BRAMs.