N-source/drain compensation effects in submicrometer LDD MOS devices

N- source/drain compensation effects in LDD devices and p-n junction leakage effects are investigated. In particular, for
L_{eff} \leq 0.3
µm, these effects will become intrinsic constraints on device minituarization. Furthermore, p-n junction leakage was found to cause refresh failures in dynamic VLSI circuits even under reduced power supply voltage.