A capacitance method to determine the gate-to-drain/Source overlap length of MOSFET's

A method is described which uses accurate measurement of gate-to-drain/source overlap capacitances to determine the gate-to-drain/ source overlap length for process control as well as device characterization. The method might also be a useful analytical tool in studying lateral dopant diffusion. Using this technique, the variation in overlap length of MOSFET's in a 4-in wafer is mapped. It is found that a significant spread of the overlap exits and is attributable to the implant shadowing by the polysilicon gate.