Characterization and suppression of drain coupling in submicrometer EPROM cells

The EPROM transistor suffers from a capacitive-coupling-based short-channel effect called drain turn-on or V
dto
that limits the maximum drain voltage. Several measurement techniques are demonstrated to characterize the V
dto
effect. An analytical model is applied to the problem to estimate the effects of process variations to suppress the phenomenon. The effect of V
dto
on scaling is discussed, and circuit and device design techiques to reduce or eliminate this problem are discussed.