Rapid isothermal processing with electron beams of small-geometry CMOS devices

Small-geometry CMOS devices with shallow n
⁺
and p
⁺
source-drain regions formed by arsenic and boron difluoride ion implantation, respectively, have been studied. Activation of implants was produced by a single rapid isothermal anneal using the multiple-scan electron-beam approach. Transistor and circuit simulations were used to determine a requirement for the source-drain region of a sheet resistance of < 100 Ω/square with a junction depth of less than 0.2 µm in 1-µm channel length devices. These values cannot be obtained by conventional furnace annealing at 950°C, but can be achieved by a single heat treatment With an e-beam. E-beam-annealed devices have a reverse-bias junction leakage similar to furnace-annealed control samples, and show improvements in short-channel effects such as short-channel threshold voltage shifts and punchthrough, without introducing other deleterious effects.