Device isolation in high-density LOCOS-isolated CMOS

Leakage paths between n- and p-channel devices in high packing density CMOS circuits fabricated using standard LOCOS isolation are investigated. Experimental results and the results of two-dimensional numerical modeling are presented for both a conventional n-well and a retrograde n-well technology. Adequate isolation for 5-V circuit operation is demonstrated for retrograde n-well structures with a 1.8-µm n
⁺
to p
⁺
diffusion separation, and for conventional n-well structures with a 2.4-µm n
⁺
to p
⁺
diffusion separation. In both cases, good latchup protection is also demonstrated using thin p
^-
on p
⁺
epitaxial material.