High holding voltage C-MOS technology with lightly doped source and drain regions

This work presents the results of measurements and simulations of n-well C-MOS structures fabricated to study the effect of reduced source-drain doping of p-channel MOSFET's on latchup triggering and holding characteristics. It is shown that lighter dopings, degrading the emitter efficiency of the parasitic p-n-p bipolar transistor, lead to improved latchup resistance that can be conveniently traded off versus the induced decrease of MOSFET transconductance.