GaInAs n-channel inversion-mode MISFET's with improved long- and short-term stability

CVD SiO
2
has been used as gate insulator for GaInAs n-channel inversion-mode MISFET's. By applying a rapid thermal annealing cycle with a maximum temperature of 700°C, the number of fast interface states could be strongly reduced, thus leading to stable device performance in the time range between 10
^-6
and 10 s. The drain current drift for longer times, however, is not affected by the annealing step. A reduction of the dielectric deposition temperature down to 250°C, however, results in improved long-term stability with a drain current decrease of only 5 percent after 10
⁴
s of operation at room temperature.