An accurate DC model for high-voltage lateral DMOS transistors suited for CACD

Double-diffused lateral MOS transistors with a drain-source breakdown voltage larger than 280 V have been integrated in an epitaxial junction isolated IC process. For these devices a four-component dc model suited for computer-aided circuit design (CACD) is developed based upon 2-D device simulation. The nonhomogeneously doped backgate is well described by two cascoded MOS transistors with different threshold voltages and gain factors. In the drift region the nonlinear dependence of the electron drift velocity on the applied electrical field is taken into account, and modulation of the on-resistance caused by a varying substrate voltage is incorporated properly. In order to model the characteristics in the entire range of operation, 10 parameters have to be optimized. The method for the parameter extraction is discussed, and a comparison between measured
I-V
characteristics and calculated values according to the model is given.