Optimization of the n+ledge channel structure for GaAs power FET's

The n
⁺
ledge channel structure used on some GaAs power FET's has several adjustable parameters. Experiments to optimize these parameters have been conducted. It is found that the gate recess should be as narrow as possible, the wide recess should be 0.5 to 0.7 µm wider than the gate, and the gate recess depth should be either ∼50 or ∼90 nm, depending on the shape of the gate recess. FET's having optimized values of these parameters had more than 1-W output power per millimeter gate width at 10 GHz along with high gain and efficiency.