Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO
2
insulator over the p
⁺
substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p
⁺
substrate before the epitaxial growth. The use of an SiO
2
sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p
⁺
substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.