Calculations of high-speed performance for submicrometer ion-implanted GaAs MESFET devices

Interest in high-speed logic devices has motivated a study of various device geometries in order to potentially improve the cutoff frequency of GaAs MESFET devices. In this paper, a two-dimensional model is used as a tool to investigate the effect of modifications of device dimensions on device performance. Modifying the device geometries by reducing the spacing between the gate and the contacts was found to improve the cutoff frequency slightly. Calculations are also presented for a device scaled to a channel length of 0.2 µm, where an f
T
of about 60 GHz is predicted.