Experimental study on current gain of BSIT

A means to improve the current gain h
FS
of the BSIT in a high drain current region has been derived from an experimental study about the dependency of the h
FS
versus drain current relationship on the channel width, the gate junction depth, and the impurity concentration in the n
^-
high-resistivity drain region. The BSIT, designed in this manner and including 9000 channels in a chip of 7 × 10 mm
²
, exhibits a current gain over 100 and high switching speeds, a rise time of 200 ns, a storage time of 200 ns and a fall time of 25 ns at a drain current of 50 A.