Interface effects of SIPOS passivation

Electrical characterization of metal-semi-insulating polycrystalline silicon (SIPOS)-Si samples have been carried out using
IV
,
C-V
, and
C-t
techniques. Bulk resistivity and interface properties have been examined. The results indicate that annealing can give rise to a current barrier at the SIPOS-Si interface that constitutes another mechanism for interface charge formation as distinct from interface states. This current barrier-induced interface charge can lead to significant spreading of the depletion zone on test diodes. With SIPOS bulk resistivity greater than 10
⁸
Ω . cm, the interface electrical properties are shown to have greater influence than bulk SIPOS properties on device behavior.