Gate oxide integrity of MOS/SOS devices

Time-dependent dielectric breakdown and ramp-voltage oxide breakdown measurements were used to evaluate the oxide integrity of MOS/SOS devices fabricated by a 3-µm process with a 500-Åthick gate oxide and dry-etched silicon islands. Field and temperature acceleration factors were determined on device arrays which ranged from 1 to 1000 devices. The measured temperature and field acceleration factors are used to give reasonable stress conditions for elimination of defective multiple device arrays without significantly altering the wear out time for nondefective arrays. Extrapolation of the data is used to suggest stress conditions and predict wear out time for 4K RAM's.